Method of etching a silicon-containing dielectric material

ABSTRACT

Disclosed herein is a method of pattern etching a layer of a silicon-containing dielectric material. The method employs a plasma source gas including CF 4  to CHF 3 , where the volumetric ratio of CF 4  to CHF 3  is within the range of about 2:3 to about 3:1; more typically, about 1:1 to about 2:1. Etching is performed at a process chamber pressure within the range of about 4 mTorr to about 60 mTorr. The method provides a selectivity for etching a silicon-containing dielectric layer relative to photoresist of 1.5:1 or better. The method also provides an etch profile sidewall angle ranging from 88° to 92° between said etched silicon-containing dielectric layer and an underlying horizontal layer. in the semiconductor structure. The method provides a smooth sidewall when used in combination with certain photoresists which are sensitive to 193 nm radiation.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention pertains to a method of etching asilicon-containing dielectric material. In particular, the inventionpertains to a method of pattern etching a layer of a silicon-containingdielectric material for use as a hard mask during subsequent patternetching of semiconductor device features having a feature size of about0.15 μm or less.

[0003] 2. Brief Description of the Background Art

[0004] Silicon-containing dielectric materials (such as silicon nitride,silicon oxide, and silicon oxynitride) are often used as hard masks forpattern etching of underlying layers in a semiconductor structure. Thesilicon-containing dielectric layer itself is typically patterned usingan overlying, patterned photoresist. Selectivity for etching thesilicon-containing dielectric layer relative to an overlying, organicphotoresist is important during the hard mask patterning step. As usedherein, the term “selectivity” or “etch selectivity” refers to a ratioof the etch rate of a first material (e.g., a silicon-containingdielectric material) to the etch rate of a second material (e.g.,photoresist) using a given plasma source gas and processing conditions.

[0005] Conventional plasma etch processes for pattern etchingsilicon-containing dielectric materials utilize a source gas which is acombination of CF₄ and CH₂F₂. While this etch chemistry typicallyprovides good (at least 1.5:1) selectivity for etching thesilicon-containing dielectric layer relative to the overlyingphotoresist, the resulting etch profile of a trench into thesilicon-containing dielectric layer is typically tapered, as shown inFIG. 2A. Because the silicon-containing dielectric layer will be used asa hard mask for subsequent pattern etching of underlying materiallayers, it is important that the patterned etch profile of thesilicon-containing dielectric layer exhibit an etched line sidewallangle, with respect to a horizontal base, which is as close to 90° aspossible (typically ranging between about 88° and 92°). Any deviationfrom a substantially 90° etch profile will be reflected in the etchprofiles of the underlying layers.

SUMMARY OF THE INVENTION

[0006] We have discovered a method of pattern etching 0.15 μm size andsmaller features into a layer of a silicon-containing dielectricmaterial, while providing good selectivity for etching thesilicon-containing dielectric layer relative to an overlyingphotoresist. The silicon-containing dielectric material is typicallysilicon nitride, but may alternatively be silicon oxide or siliconoxynitride, for example and not by way of limitation. When etching apattern of lines and spaces, a particularly smooth etched sidewallprofile and good etch profile is obtained when the method is used incombination with a photoresist which is sensitive to 193 nm radiation.

[0007] The source gas used for plasma etching the silicon-containingdielectric material includes CF₄ in combination with CHF₃. Carbontetrafluoride (CF₄) provides an excellent source of fluorine etchantspecies, while CHF₃ provides polymer generation and passivation ofexposed photoresist surfaces, extending the lifetime of the photoresist.We have discovered that a volumetric ratio of CF₄ to CHF₃ in the plasmasource gas within the range of about 2:3 to about 3:1 provides both asmooth etched sidewall surface (having a surface roughness of less than5 nm), a vertical etched line profile (exhibiting an angle ranging fromabout 88° to about 92° ), and good (about 1.5:1 or better) selectivityfor etching the silicon-containing dielectric layer relative to anoverlying photoresist. Typically, the volumetric ratio of CF₄ to CHF₃ inthe plasma source gas is within the range of about 1:1 to about 2:1.

[0008] We have also found that, in order to obtain a vertical etchedline profile, as the total gas flow to the etch processing chamber isincreased, the volumetric ratio of CF₄ to CHF₃ in the plasma source gasshould be decreased (i.e., the relative amount of CHF₃ in the plasmasource gas should be increased). By adjusting the total fluorine flow tothe chamber during the mask open process, it is possible to tune the CDpattern across the substrate wafer, which makes it possible tocompensate for non-uniformities within etch processes subsequentlyperformed on underlying layers within the semiconductor structure acrossthe wafer.

[0009] The etch method works particularly well when performed in asemiconductor processing chamber having a decoupled plasma source. Theprocess chamber pressure in such a processing chamber during etching istypically within the range of about 4 mTorr to about 60 mTorr, and moretypically within the range of about 20 mTorr to about 60 mTorr.

[0010] We have found that the etch method described above worksespecially well in combination with certain photoresists which aresensitive to 193 nm radiation, of the kind known in the art. The methodprovides a selectivity for etching a silicon-containing dielectric layerrelative to the photoresist of about 1.5:1 or better. The method alsoprovides an etched line profile sidewall angle ranging from 86° to 92°between the etched silicon-containing dielectric layer and an underlyinghorizontal layer in the semiconductor structure. In addition, the methodreduces etched sidewall roughness to about 5 nm or less, which isimportant for feature sizes less than about 0.10 μm.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1A shows a typical starting structure 100 which was used inthe example embodiments described herein. Structure 100 included thefollowing layers, from top to bottom: a patterned photoresist layer 114which is sensitive to 193 nm radiation; a patterned organic bottomanti-reflective coating (BARC) layer 112; a silicon nitride layer 110; atungsten layer 108; a polysilicon layer 106; and a gate oxide layer 104,all deposited overlying a single-crystal silicon substrate 102.

[0012]FIG. 1B shows a schematic cross-sectional front view of structure100 after pattern etching of silicon nitride layer 110, when apreviously known, comparative method is used to etch the silicon nitridelayer 110.

[0013]FIG. 1C shows a schematic front view of structure 100 afterpattern etching of silicon nitride layer 110 using an embodiment methodof the invention.

[0014]FIG. 2A shows a schematic cross-sectional front view of a siliconnitride layer 200, etched in a lines and spaces pattern, where theetched trench exhibits a tapered profile, where the trench is wider atthe top and narrower at the bottom.

[0015]FIG. 2B shows a schematic side view of the etched silicon nitridelayer 200 of FIG. 2A, which was traced from a photomicrograph.

[0016]FIG. 2C shows a schematic top view of the etched silicon nitridelayer 200 of FIG. 2A, which was traced from a photomicrograph.

[0017]FIG. 3A shows a schematic cross-sectional front view of siliconnitride layer 300 etched in a lines and spaces pattern using anembodiment method of the invention, where the etched line exhibits avertical sidewall profile, where the angle θ₃ between the sidewall and ahorizontal surface at the base of the sidewall ranges between about 86°and about 92°.

[0018]FIG. 3B shows a schematic side view of the etched silicon nitridelayer 300 of FIG. 3A, which was traced from a photomicrograph.

[0019]FIG. 3C shows a schematic top view of the etched silicon nitridelayer 300 of FIG. 3A, which was traced from a photomicrograph.

[0020]FIG. 4A is a schematic of a CENTURA® DPS II™ (Model of Apparatus)etch chamber of the kind which was used in processing the exampleembodiments described herein.

[0021]FIG. 4B is a schematic of an Applied Materials' MXP+ polysiliconetch chamber, which is an alternative example of an apparatus of thekind which can be used to carry out the etching processes describedherein, when various process conditions are adjusted.

[0022]FIG. 5A is a graph 500 showing critical dimension (CD) bias 502 asa function of radius 504 of travel from wafer center in dense etchedfeature areas when a plasma source gas composition of 300 sccm CF₄ and250 sccm CHF₃ was used to pattern etch a silicon nitride layer. Theprocess chamber pressure was 30 mTorr.

[0023]FIG. 5B is a graph 520 showing CD bias 522 as a function of radius524 of travel from wafer center in isolated etched feature areas when aplasma source gas composition of 300 seem CF₄ and 250 sccm CHF₃ was usedto pattern etch a silicon nitride layer. The process chamber pressurewas 30 mTorr.

[0024]FIG. 6A is a graph 600 showing CD bias 602 as a function of radius604 of travel from wafer center in dense etched feature areas when aplasma source gas composition of 200 sccm CF₄ and 130 sccm CHF₃ was usedto pattern etch a silicon nitride layer. The process chamber pressurewas 45 mTorr.

[0025]FIG. 6B is a graph 620 showing CD bias 622 as a function of radius624 of travel from wafer center in isolated etched feature areas when aplasma source gas composition of 200 sccm CF₄ and 130 seem CHF₃ was usedto pattern etch a silicon nitride layer. The process chamber pressurewas 45 mTorr.

[0026]FIG. 7A is a graph 700 showing CD bias 702 as a function of radius704 of travel from wafer center in dense etched feature areas when aplasma source gas composition of 200 seem CF₄ and 110 seem CHF₃ was usedto pattern etch a silicon nitride layer. The process chamber pressurewas 30 mTorr.

[0027]FIG. 7B is a graph 720 showing CD bias 722 as a function of radius724 of travel from wafer center in dense etched feature areas when aplasma source gas composition of 255 seem CF₄ and 185 seem CHF₃ was usedto pattern etch a silicon nitride layer. The process chamber pressurewas 30 mTorr.

[0028]FIG. 7C is a graph 740 showing CD bias 742 as a function of radius744 of travel from wafer center in dense etched feature areas when aplasma source gas composition of 280 seem CF₄ and 217 seem CHF₃ was usedto pattern etch the silicon nitride layer. The process chamber pressurewas 30 mTorr.

[0029]FIG. 7D is a graph 760 showing CD bias 762 as a function of radius764 of travel from wafer center in dense etched feature areas when aplasma source gas composition of 300 sccm CF₄ and 250 sccm CHF₃ was usedto pattern etch the silicon nitride layer. The process chamber pressurewas 30 mTorr.

[0030]FIG. 8 is a graph 800 showing CD bias 802 as a function of radius804 of travel from wafer center for various volumetric ratios of CF₄:CHF₃ in the plasma source gas used to pattern etch the silicon nitridelayer. The process chamber pressure was 30 mTorr. The etched featurecritical dimension was 0.13 μm.

[0031]FIG. 9 is a graph 900 showing advantageous volumetric ratios 902of CF₄ CHF₃ versus the total gas flow (CF₄ +CHF₃) 904 to the processchamber, when an Applied Materials' DPS II etch chamber is used toperform silicon nitride etching.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0032] Disclosed herein is a method of pattern etching a layer of asilicon-containing dielectric material. The method is particularlyuseful when pattern etching a silicon-containing dielectric layer usinga photoresist which is sensitive to 193 nm radiation, where thepatterned silicon-containing dielectric layer is to be subsequently usedas a hard mask for pattern etching of semiconductor device featureshaving a feature size of about 0.15 μm or less; more typically, about0.1 μm or less.

[0033] Exemplary processing conditions for performing variousembodiments of the method of the invention are set forth below. Althoughthe method embodiments described below pertain to the use of asilicon-containing dielectric material as a hard mask in the etching ofa gate structure, the etch chemistry and processing conditions describedbelow can be used any time a silicon-containing dielectric material isused as a masking layer, for example, in the etching of a trench orother semiconductor feature.

[0034] As a preface to the detailed description, it should be notedthat, as used in this specification and the appended claims, thesingular forms “a”, “an”, and “the” include plural referents, unless thecontext clearly dictates otherwise.

[0035] I. An Apparatus for Practicing the Invention

[0036] The embodiment etch methods described herein are typicallyperformed in a plasma etch chamber having a Decoupled Plasma Source(DPS) of the kind described by Yan Ye et al. at the Proceedings of theEleventh International Symposium of Plasma Processing, May 7, 1996, andas published in the Electrochemical Society Proceedings, Volume 96-12,pp. 222-233 (1996). In particular, the embodiment example etch processesdescribed herein were carried out in a CENTURA® DPS II™ plasma etchchamber available from Applied Materials, Inc., of Santa Clara, Calif.This apparatus used to carry out the etching described herein isdiscussed in detail below; however, it is contemplated that otherapparatus known in the industry may be used to carry out the invention.

[0037]FIG. 4A shows a schematic of a cross-sectional view of a CENTURA®DPS II™ plasma etch chamber 400 of the kind which was used to carry outthe etching processes described herein. During processing, a substrate422 is introduced into the chamber 400 through a slit valve 434. Thesubstrate 422 is held in place by means of a static charge generated onthe surface of an electrostatic chuck (ESC) cathode 424, by applying aDC voltage to a conductive layer located under a dielectric film on thechuck surface (not shown). Etch gases are introduced into the chamber400 by means of a gas distribution assembly 416. The etch chamber 400uses an inductively coupled plasma RF source power 402, which isconnected to an outer inductive coil 404 and an inner inductive coil 406for generating and sustaining a high density plasma 414 in plasmaprocessing region 412. Plasma source power 402 is split off into a firstpower distribution system 408, which provides power to outer coil 404,and a second power distribution system 410, which provides power toinner coil 406. The substrate 422 is biased by means of an RF source 428and matching network 426. Power to the plasma source 402 and substratebiasing means 428 are controlled by separate controllers (not shown).Etch byproducts and excess processing gases 413 are exhausted from thechamber through throttle valve 430, by means of pump 432, whichmaintains the desired process chamber pressure. The temperature of thesemiconductor substrate 422 is controlled using the temperature of theelectrostatic chuck cathode 424 upon which the substrate 422 rests.Typically, a helium gas flow is used to facilitate heat transfer betweenthe substrate and the pedestal.

[0038] Although the etch process chamber used to process the substratesdescribed in the Examples presented herein is shown in schematic in FIG.4A, one skilled in the art may use any of the etch processors availablein the industry, with some readily apparent adjustments in processconditions other than the plasma source gas compositions describedherein. For example, the method of the invention may alternatively beperformed in an etch processing apparatus wherein power to a plasmageneration source and power to a substrate biasing means are supplied bya single power supply, such as the Applied Materials' MXP or MXP+polysilicon etch chamber.

[0039]FIG. 4B is a schematic of an Applied Materials' MXP+ polysiliconetch chamber 450, which is a parallel plate plasma etch chamber of thekind which is known in the art. The MXP+ polysilicon etch chamberincludes a simplified, two-dimensional gas distribution plate 452, whichallows for more uniform gas distribution throughout the chamber. Thefocus ring 456 moves together with (rather than independently from) thecathode 458, resulting in reduced particle generation due to fewermoving parts within the apparatus. The high temperature cathode 458 hasindependent temperature control (not shown), which functions in responseto a temperature reading from pedestal temperature probe 462, whichpermits operation at a temperature in excess of the process chambertemperature. The substrate to be processed (not shown) rests on anelectrostatic chuck pedestal 460, which is joined to cathode 458.

[0040] II. Exemplary Methods of Pattern Etching a Silicon-containingDielectric Layer

[0041]FIG. 1A shows a typical starting structure 100 for performing theembodiment etching methods described herein. Structure 100 includes thefollowing layers, from top to bottom: a patterned 193 nm photoresistlayer 114; a patterned bottom anti-reflective coating (BARC) layer 112;a silicon-containing dielectric layer 110; a tungsten layer 108; apolysilicon layer 106; and a gate oxide layer 104, all overlying asingle-crystal silicon substrate 102.

[0042] The various layers in semiconductor structure 100 were depositedusing conventional deposition techniques known in the art, as follows.

[0043] Gate oxide layer 104 is generally a silicon oxide layer, whichwas formed by thermal oxidation, according to techniques known in theart. Gate oxide layer 104 had a thickness within the range of about 15 Åto 50 Å.

[0044] Polysilicon layer 106 was deposited by chemical vapor deposition(CVD), according to techniques known in the art. Polysilicon layer 106had a thickness within the range of about 500 Å to about 2000 Å.

[0045] Tungsten layer 108 was deposited by CVD, according to techniquesknown in the art. Tungsten layer 108 had a thickness within the range ofabout 300 Å to about 1000 Å.

[0046] In the Examples described below, silicon-containing dielectriclayer 110 was silicon nitride. However, silicon-containing dielectriclayer 110 may alternatively comprise silicon oxide or siliconoxynitride. Optionally, silicon-containing dielectric layer 110 may be adual layer, with an upper layer of silicon oxide and a lower layer ofsilicon nitride, by way of example and not by way of limitation.

[0047] Silicon nitride layer 110 was-deposited by low pressure CVD(LPCVD) or plasma-enhanced CVD (PECVD), according to techniques known inthe art. Silicon nitride layer 110 had a thickness within the range ofabout 1000 Å to about 2500 Å.

[0048] Antireflective coatings are used in combination with photoresiststo reduce standing waves and back-scattered light, so that the imagingwithin the photoresist can be better controlled. When the ARC layer liesbeneath the photoresist layer, it is commonly referred to as a bottomantireflective coating (BARC). In the present instance, organic BARClayer 112 was deposited by spin-on techniques known in the art. OrganicBARC layer 112 had a thickness within the range of about 500 Å to about1500 Å.

[0049] Photoresist layer 114 was a photoresist which is sensitive toradiation within the range of about 100 nm to about 200 nm. Typically,the photoresist is a chemically amplified organic, polymeric-basedcomposition which is available from a number of manufacturers, includingJSR Corporation (Tokyo, Japan); AZ Electronic Materials (Somerville,N.J.); and Shipley, Inc. (Marlboro, Mass.). A typical film thickness forsuch a photoresist ranges from about 2000 Å to about 3000 Å. Thethickness and patterning method for the photoresist layer 114 willdepend on the particular photoresist material used and the pattern to beetched in the underlying substrate. In the present instance, for etchinga pattern of lines and spaces which are less than 150 nm wide through a2000 Å thick layer of silicon nitride, the resist thickness was about3000 Å. The maximum thickness of the photoresist is limited by theaspect ratio of the photoresist being developed and the characteristicsof the photoresist used. To obtain advantageous results, the aspectratio of the photoresist being developed is typically about 4:1 or less;more typically, about 3:1 or less.

[0050] Patterned photoresist layer 114 was used as a mask to transferthe pattern to underlying BARC layer 112. Pattern etching of lines andspaces through BARC layer 112 was performed using a plasma source gasincluding CF₄ and argon. Typical process conditions for pattern etchingof organic BARC layer 112 were as follows: 100 sccm of CF₄; 100 sccm ofAr; 4 mTorr to 20 mTorr process chamber pressure; 300 W to 1000 W plasmasource power; 30 W to 100 W substrate bias power (about −60 V to −1000 Vsubstrate bias voltage); and a 40° C. to 80° C. substrate temperature.Etching time will depend on the composition and thickness of theparticular organic BARC layer being etched. For a BARC layer having athickness of about 800 °, the etch time is typically within the range ofabout 20 seconds to about 30 seconds.

[0051] III. Comparative Silicon Nitride Etch Examples

[0052] Commonly owned, copending U.S. Application Serial No. __/______(Attorney Docket No. AM-6867) (“the'___ application”), filed on the sameday as the present application, also discloses a method of patternetching feature sizes ranging from about 0.13 μm to about 0.25 μm into alayer of a silicon-containing dielectric material. The etching methodinvolves using a plasma generated from a plasma source gas comprisingabout 30 to about 70 volume % CH₂F₂, about 30 to about 70 volume % CF₄,and about 2 to about 20 volume % O₂. The plasma source gas may bediluted with an inert gas such as helium, argon, neon, xenon, orkrypton, by way of example and not by way of limitation. Often, thenonreactive diluent gas is helium. Often, the plasma source gas isselected to include about 10 to about 25 volume % CH₂F₂, about 10 toabout 25 volume % CF₄, about 2 to about 10 volume % O₂, and about 50 toabout 70 volume % helium. The method is typically performed in asemiconductor processing chamber having a decoupled plasma source. Theprocess chamber pressure during etching is typically within the range ofabout 4 mTorr to about 10 mTorr. When used in combination with aphotoresist which is sensitive to 248 nm radiation, the method providesboth good (about 2:1 or better) selectivity for etching asilicon-containing dielectric material relative to photoresist andexcellent etch profile control. The method provides a line etch profilesidewall angle ranging from 80° to 89° between the etchedsilicon-containing dielectric layer and an underlying horizontal layerin the semiconductor structure, while providing an etched sidewallsurface roughness of about 5 nm or less.

[0053] However, as semiconductor device feature sizes decrease belowabout 0.13 μm, it becomes necessary to use a photoresist that can beimaged at wavelengths of light less than about 200 nm. Popularphotoresists which are imageable by 193 nm radiation are available froma number of manufacturers, including JSR Corporation (Tokyo, Japan); AZElectronic Materials (Somerville, N.J.); and Shipley, Inc. (Marlboro,Mass.).

[0054] When we tried to use the CH₂F₂/CF₄/O₂ etch chemistry disclosed inthe '___ application (AM-6867) in combination with a photoresist forsub- 150 nm devices which is based on alicyclic polymer resin technologyto pattern etch a 0.13 μm lines and spaces pattern in a silicon nitridelayer, the result was a hard mask opening having either significantsidewall striations, a tapered profile, or both, as described in thefollowing comparative examples.

[0055] The following comparative examples were performed using thestarting structure 100 shown in FIG. 1. Thicknesses of the variouslayers were as follows: a 3000 Å thick patterned 193 nm photoresistlayer 114 (JSR Corporation, Tokyo, Japan); a 800 Å thick patternedorganic BARC layer 112; a 2000 Å thick silicon nitride layer 110; a 500Å thick tungsten layer 108; a 800 Å thick polysilicon layer 106; and a15 Å thick silicon oxide gate layer, all deposited overlying asingle-crystal silicon substrate 102.

[0056] After patterning of organic BARC layer 112, silicon nitride layer110 was etched. Silicon nitride etching was performed in an AppliedMaterials' DPS II plasma etch chamber (of the kind shown in FIG. 4).Plasma etching of silicon nitride layer 110 was performed using thefollowing plasma source gas composition and etch process conditions: 30seem CF₄; 60 sccm CH₂F₂; 5 sccm O₂; 4 mTorr process chamber pressure;1200 W plasma source power; 250 W substrate bias power; and 60° C.substrate temperature.

[0057]FIG. 1B shows a schematic front view of structure 100 afterpattern etching of silicon nitride layer 110, when etching was performedusing the CF₄/CH₂F₂ / O₂ etch chemistry and process conditions set forthabove. Note the profile of etched silicon nitride layer 110, where thetrenches 111 etched into silicon nitride layer 110 have a taperedprofile.

[0058] FIGS. 2A-2C are schematic drawings traced from photomicrographstaken of a silicon nitride layer 200, etched in a 0.20 μm lines andspaces pattern, where etching was performed using the CF₄/CH₂F₂ /O₂ etchchemistry described in the'___ application, in combination with analicyclic-based photoresist sensitive to 193 nm radiation. FIG. 2A showsa schematic cross-sectional front view of silicon nitride layer 200,when etching was performed using a plasma source gas compositionconsisting of approximately 32 volume % CF₄, 63 volume % CH₂F₂, and 5volume % O₂ etch chemistry. The etched trench 211 exhibits asubstantially tapered profile.

[0059] The '___ application teaches the addition of O₂ to the plasmasource gas for the purpose of profile control. Therefore, in hopes ofobtaining a more vertical etch profile for line 210, we performed anexperiment in which we increased the amount of O₂ in the plasma sourcegas to 14 volume % (the relative proportions of CF₄ and CH₂F₂ in thesource gas remained the same). Plasma etching of the silicon nitridelayer was performed using the following plasma source gas compositionand etch process conditions: 30 sccm CF₄; 60 sccm CH₂F₂; 15 sccm O₂; 4mTorr process chamber pressure; 1000 W plasma source power; 250 Wsubstrate bias power; and 60° C. substrate temperature.

[0060] The resulting etch profile was more vertical than that shown inFIG. 2A. However, the etched sidewall exhibited severe striation and wasparticularly rough (exhibiting a surface roughness of about 15 nm). FIG.2B shows a schematic side view of the etched silicon nitride layer 210showing the striations. FIG. 2C shows a schematic top view of the etchedsilicon nitride layer 210 of FIG. 2B. The etched line exhibits a verynon-uniform line width due to the sidewall striations.

[0061] Because the silicon-containing dielectric layer will be used as ahard mask for subsequent pattern etching of underlying material layers,it is important that the masking layer sidewall surfaces be as smooth aspossible, and that the patterned etch profile of the silicon-containingdielectric layer exhibit a sidewall angle, with respect to a horizontalbase, which is as close to 90° as possible. Any non-uniformity and/ortapering in the etch profile of the mask opening will be reflected inthe etch profiles of the underlying layers.

[0062] Therefore, we needed to a develop a method of pattern etching alayer of a silicon-containing dielectric material which provides asmooth etched feature sidewall and a vertical etch profile when used incombination with certain 193 nm photoresists, such as those which arebased on alicyclic polymer resin technology

[0063] IV. Invention Embodiment Examples

[0064] We have discovered a method of pattern etching a layer of asilicon-containing dielectric material which provides good selectivityfor etching the silicon-containing dielectric layer relative tophotoresist, a smooth etch profile, and good etch profile control, whenused in combination with certain 193 nm photoresists. The source gasused for plasma etching the silicon-containing dielectric materialincludes CF₄ in combination with CHF₃.

[0065] The following examples were performed using the startingstructure 100 shown in FIG. 1. Thicknesses of the various layers were asfollows: a 3000 Å thick patterned 193 nm photoresist layer 114 (JSRCorporation, Tokyo, Japan); a 800 Å thick patterned BARC layer 112; a2000 Å thick silicon nitride layer 110; a 500 Å thick tungsten layer108; a 800 Å thick polysilicon layer 106; and a 15 Å thick silicon oxidegate layer, all deposited overlying a single-crystal silicon substrate102.

[0066] After patterning of BARC layer 112, silicon nitride layer 110 wasetched. Silicon nitride etching was performed in an Applied Materials'DPS II plasma etch chamber (shown in FIG. 4). Silicon nitride etchprocess conditions used during each experiment are presented in TablesOne and Two, below. TABLE ONE Process Conditions Used During Etching ofSilicon Nitride Run Run Run Run Run # # # # # Process Parameter 1 2 3 45 CF₄ Flow Rate (sccm) 100 200 200 200 200 CHF₃ Flow Rate (sccm) 100 6565 85 85 Process Chamber Pressure 15 30 45 15 30 (mTorr) RF Power toInner Coil (W) 250 250 250 250 250 RF Power to Outer Coil (W) 250 250250 250 250 Total Plasma Source Power (W) 500 500 500 500 500 SubstrateBias Power (W) 100 100 100 100 100 Substrate Temperature (° C.) 60 60 6060 60 Etch Time Period (seconds) 49 54 69 58 64 Si_(x)N_(y): PRSelectivity 1.8 1.2 1.5 1.1 1.5 Etch Profile Angle (θ) 86 93 94 88 92

[0067] TABLE TWO Process Conditions Used During Etching of SiliconNitride Run Run Run Run Run # # # # # Process Parameter 6 7 8 9 10 CF₄Flow Rate (sccm) 200 200 200 200 200 CHF₃ Flow Rate (sccm) 85 110 110 4080 Process Chamber Pressure 45 15 30 45 30 (mTorr) RF Power to InnerCoil (W) 250 250 250 250 250 RF Power to Outer Coil (W) 250 250 250 250250 Total Plasma Source Power (W) 500 500 500 500 500 Substrate BiasPower (W) 100 100 100 100 100 Substrate Temperature (° C.) 60 60 60 6060 Etch Time Period (seconds) 75 60 70 61 71 Si_(x)N_(y): PR Selectivity1.5 1.1 1.5 1.3 1.4 Etch Profile Angle (θ) 93 86 89 97 95

[0068]FIG. 1C shows structure 100 after pattern etching of siliconnitride layer 110. As shown in FIG. 1C, etched silicon nitride layer 110has a substantially vertical line profile, as indicated by θ₂.

[0069] FIGS. 3A-3C are drawings based on photomicrographs taken of asilicon nitride layer 300, etched in a lines and spaces pattern, whereetching was performed using the etch chemistry and process conditions ofRun # 8 (from Table Two, above). FIG. 3A shows a schematiccross-sectional front view of silicon nitride layer 300. The etched lineexhibits a vertical sidewall profile, where the angle θ₃ between thesidewall and a horizontal surface at the base of the sidewall rangesbetween about 88° and about 92°. FIG. 3B shows a schematic side view ofthe etched silicon nitride layer 300 of FIG. 3A. Note the reduction instriation, as compared to the sidewall shown in FIG. 2B. FIG. 3C shows aschematic top view of the etched silicon nitride layer 300 of FIG. 3A.The etched line shown in FIG. 3C exhibits a more uniform line width thanthe etched line of FIG. 2C.

[0070] When pattern etching a silicon nitride layer using the CH₂F₂/CF₄/O₂ etch chemistry disclosed in the '___ application in combination witha 193 nm photoresist which is based on alicyclic polymer resintechnology, we found that the polymer generated on etched surfaces as aresult of the combination of the CH₂F₂ etchant gas with species from thephotoresist was very soft. The soft polymer produced distortions in thephotoresist pattern profile during etching, inducing the non-uniformsilicon nitride sidewall 210 shown in FIGS. 2B, and evident from the topview shown in FIG. 2C. It is also possible that the photoresist itselfis distorting during the silicon nitride etch process, due to thecomposition of the alicyclic polymer binders of the photoresist whichare not able to pack as densely together as some other types ofpolymeric binder resins, such as those based on blockedpolyhydroxystyrene with methacrylate (available from Shipley, Inc.,Marlboro, Mass.), which have not demonstrated this deformation problem.Distortion of the photoresist during the etch process can result in thestriation and non-uniformity of the silicon nitride sidewall seen inFIGS. 2B and 2C.

[0071] It is our conclusion that the use of the less hydrogen-rich, CHF₃polymer-forming etchant gas in combination with the 193 nm photoresistbased on alicyclic polymer resin technology resulted in the generationof a less porous or more dense polymer on the photoresist surface. Evenat a reduced thickness, this polymer can sustain plasma etching evenly,and this was mirrored in the smooth, unstriated silicon nitride sidewall300, illustrated in FIG. 3B, and evidenced in the top view shown in FIG.3C. A smooth sidewall on the silicon nitride hard mask surface resultsin more uniform etch profiles of subsequently etched underlying layers.

[0072] In general, we found that decreasing the volumetric ratio of CF₄to CHF₃ in the plasma source gas and increasing the process chamberpressure resulted in better selectivity for etching silicon nitriderelative to photoresist, and less faceting of the photoresist.Advantageous results were achieved at volumetric ratios of CF₄ to CHF₃within the range of about 1:1 to about 2:1, and at process chamberpressures within the range of about 20 mTorr to about 60 mTorr.

[0073] We also performed a series of experiments to examine etchuniformity across the surface of the substrate when the volumetric ratioof CF₄ to CHF₃ was varied. We measured the CD bias in dense and isolatedfeature areas of a silicon substrate wafer when the following etchchemistry and process conditions were used to pattern etch the siliconnitride layer: 300 sccm CF₄; 250 sccm CHF₃; 30 mTorr process chamberpressure; 500 W plasma source power; 100 W substrate bias power; and 60°C. substrate temperature. As used herein, the term “CD bias” refers tothe difference between the line width of an etched line and the linewidth in the photoresist used to pattern the line. The term “densefeature area” refers to an area on the substrate where features arespaced closely together; the term “isolated feature area” refers to anarea on the substrate where features are spaced relatively far apart.

[0074]FIG. 5A is a graph 500 showing CD bias 502 as a function of radius504 from wafer center in dense feature areas of the substrate. As usedherein, the term “radius” refers to the distance of travel from thecenter of a circular substrate wafer toward the edge of the wafer. FIG.5B is a graph 520 showing CD bias 522 as a function of radius 524 fromwafer center in isolated feature areas of the substrate. Referring toFIG. 5A, the average CD bias in dense feature areas was −0.0143 μm, witha range of 0.0114 μm. Referring to FIG. 5B, the average CD bias inisolated feature areas was −0.0033 μm, with a range of 0.0175 μm.

[0075] We also measured the CD bias in dense and isolated feature areasof a silicon substrate wafer when the following etch chemistry andprocess conditions were used to pattern etch the silicon nitride layer:200 sccm CF₄; 130 sccm CHF₃; 45 mTorr process chamber pressure; 500 Wplasma source power; 100 W substrate bias power; and 60° C. substratetemperature. FIG. 6A is a graph 600 showing CD bias 602 as a function ofradius 604 from wafer center in dense feature areas of the substrate.FIG. 6B is a graph 620 showing CD bias 622 as a function of radius 624from wafer center in isolated feature areas of the substrate. Referringto FIG. 6A, the average CD bias in dense feature areas was −0.0167 μm,with a range of 0.0131 μm. Referring to FIG. 6B, the average CD bias inisolated feature areas was −0.0045 μm, with a range of 0.0183 μm.

[0076] A comparison of the experimental results illustrated in FIGS. 5and 6 indicates that slightly better etch uniformity was achieved with alower volumetric ratio of CF₄ to CHF₃ (1.2:1 in FIG. 5 versus 1.5:1 inFIG. 6) and a lower process chamber pressure (30 mTorr in FIG. 5 versus45 mTorr in FIG. 6).

[0077] We performed another series of experiments to examine etchuniformity in dense feature areas of the substrate when the volumetricratio of CF₄ to CHF₃ was varied. FIG. 7A is a graph 700 showing CD bias702 as a function of radius 704 from wafer center in dense feature areasof the substrate when a plasma source gas composition of 200 sccm CF₄and 110 sccm CHF₃ was used to pattern etch the silicon nitride layer.FIG. 7B is a graph 720 showing CD bias 722 as a function of radius 724in dense feature areas of the substrate when a plasma source gascomposition of 255 sccm CF₄ and 185 sccm CHF₃ was used to pattern etchthe silicon nitride layer. FIG. 7C is a graph 740 showing CD bias 742 asa function of radius 744 from wafer center in dense feature areas of thesubstrate when a plasma source gas composition of 280 sccm CF₄ and 217sccm CHF₃ was used to pattern etch the silicon nitride layer. FIG. 7D isa graph 760 showing CD bias 762 as a function of radius 764 in densefeature areas of the substrate when a plasma source gas composition of300 sccm CF₄ and 250 sccm CHF₃ was used to pattern etch the siliconnitride layer. Other process conditions were held constant, as follows:30 mTorr process chamber pressure; 500 W plasma source power; 100 Wsubstrate bias power; and 60/20 C. substrate temperature.

[0078] Referring to FIG. 7A, the average CD bias in dense feature areaswas −0.015 μm, with a range of 0.019 μm. Referring to FIG. 7B, theaverage CD bias in dense feature areas was −0.003 μm, with a range of0.013 μm. Referring to FIG. 7C, the average CD bias in dense featureareas was −0.01 μm, with a range of 0.008 μm. Referring to FIG. 7D, theaverage CD bias in dense feature areas was −0.009 μm, with a range of0.012 μm.

[0079] In general, the plasma source gas composition of 280 sccm CF₄ and217 sccm CHF₃ (1.3:1 CF₄:CHF₃) provided the best CD uniformity (averageCD bias -0.01 μm, with a range of 0.008 μm), as shown in FIG. 7C.

[0080] During etching, etch process byproducts build up on etchedfeature surfaces. The amount of etch byproduct build-up typically variesfrom one area of the substrate wafer to another (for example, from thecenter to the edge of the wafer). The longer the residence time of etchgases and etch process byproducts within the plasma processing region412 of the etch chamber 400 (shown in FIG. 4A), the greater the amountof etch byproduct buildup. If the residence time is too long, etchbyproducts may build up disproportionately on certain areas of thewafer, thereby affecting CD uniformity. The residence time of etch gasesand etch byproducts within the plasma processing region can be decreasedby increasing the total flow rate of gases into the chamber, andincreasing the pumping rate for removal of gases from the chamber.Decreasing the residence time can prevent excessive etch byproductbuild-up product in certain areas of the wafer, providing a more uniformCD distribution.

[0081] An important parameter for the CF₄/CHF₃ etch process is the totalflow of fluorine-containing species into the processing chamber. Wefound that increasing the total gas flow to the chamber whilemaintaining a fixed ratio of CF₄ to CHF₃ results in an undercut etchprofile (i.e., an etch profile angle greater than about 92°). Therefore,in order to obtain a vertical profile, the relative amount of CHF₃ inthe plasma source gas needs to be increased (i.e., the volumetric ratioof CF₄ to CHF₃ in the plasma source gas should be decreased) as thetotal gas flow is increased. As a result of increasing the relativeamount of CHF₃ in the plasma source gas, the selectivity for etchingsilicon nitride relative to the photoresist increases, due to theincreased presence of passivating species in the plasma.

[0082]FIG. 8 is a graph 800 showing CD bias 802 as a function of radius804 from wafer center for various volumetric ratios of CF₄:CHF₃ in theplasma source gas used to etch the silicon nitride layer. As the totalgas flow to the chamber increases, at a constant chamber pressure, theCD bias distribution changes from more CD loss at the edge of thesubstrate wafer to more CD loss at the center of the substrate wafer.This is consistent with etch rate data, which show a higher etch rate atthe wafer center at high total gas flow rates. Referring again to FIG.8, the most advantageous condition for CD bias uniformity was obtainedusing a plasma source gas composition comprising 280 sccm CF₄ and 217seem CHF₃.

[0083] As illustrated in FIG. 8, as the volumetric ratio of CF₄ :CHF₃ inthe plasma source gas varies, the CD bias distribution across thesubstrate wafer changes. As a result, each particular plasma source gascomposition has its own “signature” CD bias distribution. It istherefore possible to tune the CD uniformity across the substrate waferby selecting a plasma source gas composition having a particularsignature which compensates for CD non-uniformities of etch processessubsequently performed on underlying layers within the semiconductorstructure.

[0084]FIG. 9 is a graph 900 showing advantageous volumetric ratios 902of CF₄ CHF₃ versus the total gas flow (CF₄ +CHF₃) 904 to the chamber,when an Applied Materials' DPS II etch chamber is used to performsilicon nitride etching.

[0085] According to the present method embodiment, etching of asilicon-containing dielectric material is typically performed using aplasma generated from a source gas which includes about 50 to about 75volume % CF₄, and about 25 to about 50 volume % CHF₃. Often, the plasmasource gas is selected to include about 50 to about 65 volume % CF₄, andabout 35 to about 50 volume % CHF₃.

[0086] If necessary to decrease the amount of passivation (for example,if there is too much CHF₃ in the plasma source gas), the plasma sourcegas composition may optionally include a nonreactive diluent gas such ashelium, argon, neon, xenon, or krypton. Most typically, the nonreactivediluent gas is helium. The use of argon is less preferred, because itcan lead to deformation of the photoresist, which will subsequentlyaffect the etch profile of underlying layers within the semiconductorstructure.

[0087] The etch method is typically performed in a semiconductorprocessing chamber having a decoupled plasma source. Typical processconditions for etching of a silicon-containing dielectric material,according to the present method embodiment, are provided in Table Three,below: TABLE THREE Typical Process Conditions for Etching of aSilicon-Containing Dielectric Material Range of Typical AdvantageousProcess Process Known Process Process Parameter Conditions ConditionsConditions CF₄ Flow Rate (sccm)  50-600 100-300 200-300 CHF₃ Flow Rate(sccm)  30-600  30-300 100-300 He Flow Rate (sccm)  0-500  0-100  0-100Total Gas Flow (sccm)  100-1000 130-600 300-600 Ave. Residence Time(sec)  1-10 1-6 2-6 Process Chamber Pressure  2-200  4-60 20-60 (mTorr)Plasma Source Power (W)  200-1200 300-800 300-800 Substrate Bias Power(W)   0-1500  50-200  50-200 Plasma Density (e⁻/cm³)  1 × 10¹⁰-  1 ×10¹⁰-  1 × 10¹⁰- 1 × 10¹³ 1 × 10¹³ 1 × 10¹³ Substrate Temperature 10-8020-60 20-60 (° C.) Etch Time Period (seconds)  10-100  40-100  40-100

[0088] We have discovered that a volumetric ratio of CF₄ to CHF₃ in theplasma source gas within the range of about 2:3 to about 3:1 providesboth a smooth etched sidewall surface (having a surface roughness ofless than 5 nm), a vertical etch profile (exhibiting an angle rangingfrom about 88° to about 92°), and good (about 1.5:1 or better)selectivity for etching the silicon-containing dielectric layer relativeto an overlying photoresist. Typically, the volumetric ratio of CF₄ toCHF₃ in the plasma source gas is within the range of about 1:1 to about2:1.

[0089] The present method is particularly useful in the pattern etchingof a silicon-containing dielectric layer which is to be subsequentlyused as a hard mask for pattern etching of semiconductor device featureshaving a feature size of about 0.15 μm or less; more typically, about0.1 μm or less. The method provides a selectivity for etching asilicon-containing dielectric layer relative to such a photoresist ofabout 1.5:1 or better. The method also provides an etch profile sidewallangle ranging from 88° to 92° between the etched silicon-containingdielectric layer and an underlying horizontal layer in the semiconductorstructure. In addition, the method reduces etched sidewall roughness toabout 5 nm or less.

[0090] Although the Examples above are described with reference to theuse of a silicon-containing dielectric material as a hard mask in theetching of a gate structure, the etch chemistry and processingconditions described above can be used any time a silicon-containingdielectric material is used as a masking layer, for example, in theetching of a shallow trench or other semiconductor feature.

[0091] Although the Examples above are described with reference to theuse of an ArF photoresist for sub −150 nm devices which is based onalicyclic polymer resin technology, the method of the invention isexpected to solve problems with patterned photoresist deformation duringetching for photoresists imageable within the range of about 100 nm toabout 200 nm. In particular, the present method is expected to workespecially well in solving this problem for photoresists in generalwhich are based on alicyclic polymer resin (or similar) technology.

[0092] The above described exemplary embodiments are not intended tolimit the scope of the present invention, as one skilled in the art can,in view of the present disclosure expand such embodiments to correspondwith the subject matter of the invention claimed below.

We claim:
 1. A method of pattern etching a layer of a silicon-containingdielectric material on a semiconductor substrate, wherein a patternedphotoresist layer overlies said silicon-containing dielectric layer,said method comprising exposing said silicon-containing dielectric layerto a plasma generated from a source gas comprising CF₄ and CHF₃, whereina volumetric ratio of CF₄ to CHF₃ is within a range of about 2:3 toabout 3:1.
 2. The method of claim 1, wherein said silicon-containingdielectric material is selected from the group consisting of siliconnitride, silicon oxide, silicon oxynitride, and combinations thereof. 3.The method of claim 1, wherein a volumetric ratio of CF₄ to CHF₃ iswithin the range of about 1:1 to about 2:1.
 4. The method of claim 1,wherein said plasma source gas composition comprises about 50 to about75 volume % CF₄, and about 25 to about 50 volume % CHF₃.
 5. The methodof claim 4, wherein said plasma source gas composition comprises about50 to about 65 volume % CF₄, and about 35 to about 50 volume % CHF₃. 6.The method of claim 1, wherein said photoresist is sensitive to 193 nmradiation.
 7. The method of claim 1, wherein said photoresist is basedon alicyclic polymer resin technology.
 8. The method of claim 1, whereinsaid silicon-containing dielectric layer is used as a hard mask duringpattern etching of an underlying semiconductor structure, wherein saidsemiconductor structure includes features having a feature size of about0.15 μm or less.
 9. The method of claim 1, wherein saidsilicon-containing dielectric layer has a thickness within the range ofabout 1000 Å to about 2500 Å.
 10. The method of claim 1, wherein etchingis performed at a process chamber pressure within the range of about 4mTorr to about 60 mTorr.
 11. The method of claim 10, wherein etching isperformed at a process chamber pressure within the range of about 20mTorr to about 60 mTorr.
 12. The method of claim 1, wherein said methodis performed in a semiconductor processing chamber having a decoupledplasma source.
 13. The method of claim 1, wherein said method provides aselectivity for etching said silicon-containing dielectric layerrelative to said photoresist of at least 1.5:1.
 14. The method of claim1, wherein said method provides an etch profile sidewall angle rangingfrom 88° to 92° between said etched silicon-containing dielectric layerand an underlying horizontal layer.
 15. The method of claim 1, whereinsaid method provides an etched sidewall roughness of about 5 nm or less.16. A method of pattern etching a layer of silicon nitride on asemiconductor substrate, wherein a patterned photoresist layer overliessaid silicon nitride layer, said method comprising exposing said siliconnitride layer to a plasma generated from a source gas comprising CF₄ andCHF₃, wherein a volumetric ratio of CF₄ to CHF₃ is within a range ofabout 2:3 to about 3:1.
 17. The method of claim 1, wherein a volumetricratio of CF₄ to CHF₃ is within the range of about 1:1 to about 2:1. 18.The method of claim 1, wherein said plasma source gas compositioncomprises about 50 to about 75 volume % CF₄, and about 25 to about 50volume % CHF_(3.)
 19. The method of claim 18, wherein said plasma sourcegas composition comprises about 50 to about 65 volume % CF₄, and about35 to about 50 volume % CHF₃.
 20. The method of claim 1, wherein saidphotoresist is sensitive to 193 nm radiation.
 21. The method of claim 1,wherein said photoresist is based on alicyclic polymer resin technology.22. The method of claim 1, wherein said silicon nitride layer is used asa hard mask during pattern etching of an underlying semiconductorstructure, wherein said semiconductor structure includes features havinga feature size of about 0.15 μm or less.
 23. The method of claim 1,wherein said silicon nitride layer has a thickness within the range ofabout 1000 Å to about 2500 Å.
 24. The method of claim 1, wherein etchingis performed at a process chamber pressure within the range of about 4mTorr to about 60 mTorr.
 25. The method of claim 24, wherein etching isperformed at a process chamber pressure within the range of about 20mTorr to about 60 mTorr.
 26. The method of claim 1, wherein said methodis performed in a semiconductor processing chamber having a decoupledplasma source.
 27. The method of claim 1, wherein said method provides aselectivity for etching said silicon nitride layer relative to saidphotoresist of at least 1.5:1.
 28. The method of claim 1, wherein saidmethod provides an etch profile sidewall angle ranging from 88° to 92°between said etched silicon nitride layer and an underlying horizontallayer.
 29. The method of claim 1, wherein said method provides an etchedsidewall roughness of about 5 nm or less.